Search results for " MCML"

showing 2 items of 2 documents

A Methodology for the Design of MOS Current-Mode Logic Circuits

2010

In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitan…

EngineeringPower–delay productbusiness.industryCircuit designFan-outMOS current-mode logic MCML low-power design power-delay productSettore ING-INF/01 - ElettronicaCapacitanceElectronic Optical and Magnetic MaterialsLow-power electronicsElectronic engineeringCurrent-mode logicElectrical and Electronic EngineeringMATLABbusinesscomputerHardware_LOGICDESIGNcomputer.programming_languageElectronic circuitIEICE Transactions on Electronics
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Power-aware design of MCML logarithmic adders

2010

This paper describes the low-power design of a MOS current-mode logarithmic adder. The adder utilizes the Brent-Kung tree structure. The design strategy adopted is very simple and effective. Moreover, it can be utilized also for other types of logarithmic adders. To validate it, several adders were designed in a TSMC CMOS 130nm technology. Results of simulations indicate that the proposed methodology offers a good starting point before fine-tuning the design by SPICE simulations. Finally, the tradeoff that can be realized between performance and power consumption is discussed.

MOS current-mode logic MCML logarithmic adders Brent-Kung tree structureSettore ING-INF/01 - Elettronica
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